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MOTOROLA Freescale Semiconductor, Inc.
Semiconductor Technical Data
Order this document by APD Marketing Rev 5.6, 23th July 02
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System Basis Chip Lite with Low Speed Fault Tolerant CAN Interface
The MC33889 is a monolithic integrated circuit combining many functions frequently used by automotive ECUs. It incorporates a low speed fault tolerant CAN physical interface. Main features: * Vdd1: 5V Low drop voltage regulator, current limitation, over temperature detection, monitoring and reset function. Total current capability 200mA. * V2: Tracking function of Vdd1 regulator. Control circuitry for external bipolar ballast transistor for high flexibility in choice of peripheral voltage and current supply. * Four operational modes: normal, stand-by, stop and sleep modes. * Low stand-by current consumption in stop and sleep modes * Built in Low speed 125KBaud fault tolerant CAN physical interface, compatible with Motorola MC33388. * External high voltage wake-up input, associated with HS1 Vbat switch * 150mA output current capability for HS1 Vbat switch allowing drive of external switches pull up resistors or relays * Vsup monitoring and failure detection * DC Operating voltage from 5 to 27V * 40V maximum transient voltage * Programmable software time out and window watchdog * Separate outputs for Watchdog time out signal (WDOGB) and Reset (Reset). * Wake up capabilities: wake up input, programmable cyclic sense, forced wake up, CAN interface, SPI (CSB pin) and stop mode over current. * Interface with MCU through 4 Mhz SPI. * SO28WB package with thermal enhanced lead frame.
PC33889
PASS3
System Basis Chip Lite
SILICON MONOLITHIC INTEGRATED CIRCUIT
Freescale Semiconductor, Inc...
DW SUFFIX
PLASTIC PACKAGE CASE 751F SO-28
PIN CONNECTIONS
Simplified Block Diagram
Q1 Vbat V2CTRL Vsup V2
5V
Vsup monitor CAN supply Dual Voltage Regulator 5V/200mA Vdd1 Monitor Mode control
HS1 control
Vdd1
5V/200mA
RX TX Vdd1 Reset INTB GND GND GND GND V2ctrl Vsup HS1 L0 L1
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
WDOGB CSB MOSI MISO SCLK GND GND GND GND CANL CANH Rtl Rth V2
HS1
L0 L1
Oscillator
Programmable wake-up input
Interrupt Watchdog Reset
INTB WDOGB
Reset
MOSI SCLK MISO CSB V2 Txd Rxd Gnd
Device
SPI Interface
Vsup Rrth Rth CAN H CAN L Rrtl Rtl Low Speed 125Kbit/s Fault Tolerant CAN Physical Interface
ORDERING INFORMATION
Operating Temperature Range Package
PC33889DW This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. For More Information On (c) Motorola, Inc., 2002. All rights reserved.
TA = -40 to 125C
SO-28
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Freescale Semiconductor, Inc.
1 MAXIMUM RATINGS
Ratings ELECTRICAL RATINGS Symbol Min Typ Max Unit
PC33889
Supply Voltage at Vsup - Continuous voltage - Transient voltage (Load dump) Logic Inputs (Rx, Tx, MOSI, MISO, CSB, SCLK, Reset, WDOGB, INTB) Output current Vdd1 HS1 - voltage - output current ESD voltage (HBM 100pF, 1.5k) - CANL, CANH, Rtl, Rth, HS1, L0, L1 - All other pins ESD voltage (Machine Model) All pins L0, L1 - DC Input voltage - DC Input current - Transient input current (according to ISO7637 specification) and with external component tbd. CAN related pins: CANH, CANL, RTL, RTH, Tx, Rx (refer to CAN section)
THERMAL RATINGS
V Vsup Vsup Vlog -0.3 27 40 Vdd1+0.3 V
- 0.3
I
Internally limited
A
V I Vesdh
-0.2 Internally limited
Vsup+0.3
V A kV
-4 -2 Vesdm Vwu DC -0.3 -2 tbd -200
4 2 200 V
Freescale Semiconductor, Inc...
40 2 tbd
V mA mA
Junction Temperature Storage Temperature Ambient Temperature (for info only) Thermal resistance junction to gnd pin (note 1)
Tj Ts Ta Rthj/p
- 40 - 55 - 40
+150 +165 +125 20
C C C C/W
Note 1: gnd pins 6,7,8,9,20, 21, 22, 23. Figure 1. Transient test pulse for L0 and L1 inputs
1nF Lx 10 k
Transient Pulse Generator (note) Gnd
Gnd
note: Waveform in accordance to ISO7637 part1, test pulses 1, 2, 3a and 3b.
PC33889
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2
ELECTRICAL CHARACTERISTICS
(Vsup From 5.5V to 18V and Tj from -40C to 125C) unless otherwise noted. For all pins except can related pins
PC33889
Characteristics Description Vsup pin (Device power supply) Nominal DC Voltage range Extended DC Voltage range 1 Extended DC Voltage range 2 Input Voltage during Load Dump Input Voltage during jump start Supply Current in Sleep Mode (note 2,4)
Vsup
Symbol Min Typ Max
Unit
Conditions
5.5 4.5 18
18 5.5 27 40 27 75 tbd
V V V V V uA Reduced functionality (note 1) (note 3) Load dump situation Jump start situation Vdd1 & V2 off, Vsup<12V, oscillator running (note 5) excluding CAN current Vdd1 & V2 off, Vsup<12V oscillator not running (note5) excluding CAN current, Vdd1 & V2 off, Vsup>12V oscillator running (note 5) excluding CAN current Iout at Vdd1 =10mA, CAN recessive state or disabled Iout at Vdd1 =10mA, CAN recessive state or disabled Vdd1 on (note 6), Vsup<12V oscillator running (note 5) excluding CAN current, Vdd1 on (note 6), Vsup<12V oscillator not running (note 5) excluding CAN current Vdd1 on (note6), Vsup>12 oscillator running (note 5) excluding CAN current
Vsup-ex1 Vsup-ex2
VsupLD VsupJS Isup (sleep1)
Supply Current in Sleep Mode (note 2,4)
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Isup (sleep2)
60
tdb
uA
Supply current in sleep mode (note 2,4)
Isup (sleep3) Isup(stdby) Isup(norm)
150
tbd
uA
Supply Current in Stand-by Mode (note 2,4) Supply Current in Normal Mode (note 2) Supply Current in Stop mode (note 2,4) I out Vdd1 <2mA Supply Current in Stop mode (note 2,4) Iout Vdd1 < 2mA Supply Current in Stop mode (note 2,4) Iout Vdd1 < 2mA Supply Fail Flag internal threshold Supply Fail Flag hysteresis Battery fall early warning threshold Battery fall early warning hysteresis
15 15 120 tbd
mA mA uA
Isup (stop1) Isup (stop2) Isup (stop3) Vthresh Vdet hyst BFew BFewh 5.9 0.1 1.5
110
tbd
uA
180
tbd
uA
3 1 6.1 0.2
4
V V guaranteed by design In normal & standby mode In normal & standby mode, guaranteed by design
6.3 0.3
V V
note 1: Vdd1>4V, reset high, logic pin high level reduced, device is functional. note 2: current measured at Vsup pin. note 3: Device is fully functional. All modes available and operating, Watchdog, HS1 turn ON turn OFF, CAN cell operating, L0 and L1 inputs operating, SPI read write operation. Over temperature may occur. note 4: Excluding the CAN cell current. An additional 30uA typical must be added to specified value. note 5: Oscillator running means "Forced Wake Up" or "Cyclic Sense" or "Software Watchdog" timer activated. note 6: Vdd is ON with2mA typical output current capability. Vdd1 (external 5V output for MCU supply). Idd1 is the total regulator output current. Vdd specification with external capacitor C>=22uF and ESR<1O ohm. Vdd1 Output Voltage Vdd1 Output Voltage Drop Voltage Vsup>Vddout Drop Voltage Vsup>Vddout, limited output current Idd1 Output Current Vdd1 Output Voltage in stop mode Vdd1out Vdd1out Vdd1drop Vdd1dp2 Idd1 Vddstop 200 4,75 4,9 4 0.2 0,1 270 5,00 0,5 0,25 350 5,25 5 5,1 V V V V mA V Idd1 from 2 to 200mA 5.5V< Vsup <27V Idd1 from 2 to 200mA 4.5V< Vsup <5.5V Idd1 = 200mA Idd1 = 50mA 4.5V< Vsup <27V Internally limited Iout < 2mA
PC33889
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(Vsup From 5.5V to 18V and Tj from -40C to 125C) unless otherwise noted. For all pins except can related pins
PC33889
Characteristics Description Idd1 stop output current to wake up SBC Idd1 stop output current to wake up SBC Idd1 over current wake deglitcher (with Idd1s-wu1 selected) Idd1 over current wake deglitcher (with Idd1s-wu2 selected) Thermal Shutdown Over temperature pre warning Temperature Threshold difference Reset threshold 1 Reset threshold 2 Reset duration Vdd1 range for Reset Active Reset Delay Time Line Regulation Line Regulation Load Regulation Thermal stability Symbol Min Idd1s-wu1 Idd1s-wu2 Idd1-dglt1 Idd1-dglt2 Tsd Tpw Tsd-Tpw Rst-th1 Rst-th2 reset-dur Vddr td LR1 LR2 LD ThermS 160 130 20 4.5 4.1 0.85 1 5 5 10 20 5 20 25 25 50 4.6 4.2 1 2 10 40 Typ 3.5 14 75 150 190 160 40 4.7 4.3 2 ms V us mV mV mV mV measured at 50% of reset signal. Guaranteed by design 9VC C C
Unit
Conditions Selectable by SPI. Default value after reset. Selectable by SPI Guaranteed by design Guaranteed by design Normal or standby mode VDDTEMP bit set
Selectable by SPI. Default value after reset. Selectable by SPI
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V2 tracking voltage regulator note 7: V2 specification with external capacitor - option 1: C>=22uF and ESR<1O ohm - option2: 1uFPC33889
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(Vsup From 5.5V to 18V and Tj from -40C to 125C) unless otherwise noted. For all pins except can related pins
PC33889
Characteristics Description Low Level Output Voltage (I0=1.5mA) High Level Output Voltage (I0=-250uA) INT Pin Low Level Output Voltage (I0=1.5mA) High Level Output Voltage (I0=-250uA) HS1: 150mA High side output pin Rdson at Tj=25C, and Iout -150mA Rdson at Tj=125C, and Iout -150mA Rdson at Tj=125C, and Iout -120mA Output current limitation Over temperature Shutdown Leakage current Output Clamp Voltage at Iout= -1mA Cyclic sense period (refer to SPI) Cyclic sense On time (refer to SPI) Timing accuracy (cyclic sense period and on time) L0 and L1 inputs L0 Negative Switching Threshold Vth0n 1.7 2 2 2.2 2.5 2.5 2 2.5 2.7 2.7 3 3.5 0.6 tbd Input current Wake up Filter Time (enable/disable option on L0 input) DIGITAL INTERFACE TIMING SPI operation frequency SCLK Clock Period SCLK Clock High Time SCLK Clock Low Time Falling Edge of CS to Rising Edge of SCLK Falling Edge of SCLK to Rising Edge of CS MOSI to Falling Edge of SCLK Falling Edge of SCLK to MOSI MISO Rise Time (CL = 220pF) MISO Fall Time (CL = 220pF) Freq tpCLK twSCLKH twSCLKL tlead tlag tSISU tSIH trSO tfSO 250 125 125 100 100 40 40 50 50 25 25 25 25 50 50 4 MHz ns ns ns ns ns ns ns ns ns Iin -10 8 20 10 38 uA us tbd tbd tbd tbd 2.5 3 3.2 3.3 4 4.2 3 3 3.1 4 4 4.1 3 3.6 3.7 3.8 4.6 4.7 1.3 V 5.5VC
Symbol Min Vol Voh 0 Vdd1-0.9 Typ Max 0.9 Vdd1
Unit V
Conditions 5.5vVol Voh
0 Vdd1-0.9
0.9 Vdd1
V
Vsup>9V Vsup>9V 5.5VFreescale Semiconductor, Inc...
uA V ms us % no inductive load drive capability in sleep and stop modes in sleep and stop modes in sleep and stop mode
L0 Positive Switching Threshold
Vth0p
V
L1 Negative Switching Threshold
Vth1n
V
L1 Positive Switching Threshold
Vth1p
V
Hysteresis
Vhyst
V
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(Vsup From 5.5V to 18V and Tj from -40C to 125C) unless otherwise noted. For all pins except can related pins
PC33889
Characteristics Description Time from Falling or Rising Edges of CS to: - MISO Low Impedance - MISO High Impedance Time from Rising Edge of SCLK to MISO Data Valid Symbol Min tSOEN tSODIS tvalid Typ Max 50 50 50 ns 0.2 V1SO 0.8V1, CL=200pF Unit Conditions
ns
STATE MACHINE TIMING note 1: delay starts at rising edge of CSB (end of SPI command) and start of Turn on or Turn off of HS1 or V2. Delay between CSB low to high transition (at end of SPI stop command) and Stop or sleep mode activation Interrupt low level duration Internal oscillator frequency Tcsb-stop Tint Osc-f1 18 7 10 100 34 13 us us kHz Guaranteed by design detected by V2 off SBC in stop mode All modes except Sleep and Stop, guaranteed by design Sleep and Stop modes, guaranteed by design Normal and standby modes Normal and standby modes Normal and standby modes Normal and standby modes Normal and standby modes Normal request mode Stop mode Stop mode Stop mode Stop mode Stop mode Sleep and stop modes Sleep and stop modes Sleep and stop modes Sleep and stop modes Sleep and stop modes Sleep and stop modes Sleep and stop modes Sleep and stop modes in sleep and stop modes threshold and condition to be added in sleep and stop mode Normal or standby mode Vsup>9V Normal or standby mode Vsup>9V Standby mode Normal modes Normal request mode
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Internal low power oscillator frequency Watchdog period 1 Watchdog period 2 Watchdog period 3 Watchdog period 4 Watchdog period accuracy Normal request mode timeout Watchdog period 1 - stop Watchdog period 2- stop Watchdog period 3 - stop Watchdog period 4 - stop Stop mode watchdog period accuracy Cyclic sense/FWU timing 1 Cyclic sense/FWU timing 2 Cyclic sense/FWU timing 3 Cyclic sense/FWU timing 4 Cyclic sense/FWU timing 5 Cyclic sense/FWU timing 6 Cyclic sense/FWU timing 7 Cyclic sense/FWU timing 8 Cyclic sense On time
Osc-f2 Wd1 Wd2 Wd3 Wd4 F1acc NRtout Wd1stop Wd2stop Wd3stop Wd4stop F2acc CSFWU1 CSFWU2 CSFWU3 CSFWU4 CSFWU5 CSFWU6 CSFWU7 CSFWU8 Ton 8.58 39.6 88 308 -12 308 6.82 31.5 70 245 -30 3.22 6.47 12.9 25.9 51.8 66.8 134 271 200
100 9.75 45 100 350 10.92 50.4 112 392 12 350 9.75 45 100 350 392 12.7 58.5 130 455 30 4.6 9.25 18.5 37 74 95.5 191 388 350 5.98 12 24 48.1 96.2 124 248 504 500
kHz ms ms ms ms % ms ms ms ms ms % ms ms ms ms ms ms ms ms us
Cyclic sense/FWU timing accuracy Delay between SPI command and HS1 turn on (note 1) Delay between SPI command and HS1 turn off (note 1) Delay between SPI and V2 turn on (note 1) Delay between SPI and V2 turn off (note 1) Delay between Normal Request and Normal mode, after W/D trigger command
Tacc Ts-HSon Ts-HSoff Ts-V2on Ts-V2off Ts-NR2N
-30
+30 22 22
% us us us us us
9 9 15 35
22 22 70
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Delay between SPI and "CAN normal mode" Delay between SPI and "CAN sleep mode" Delay between CSB wake up (CSB low to high) and SBC normal request mode (Vdd1 on & reset high) Delay between CSB wake up (CSB low to high) and first accepted SPI command Delay between INT pulse and 1st SPI command accepted Ts-CANn Ts-CANs 10 10 us us SBC Normal mode guaranteed by design SBC Normal mode guaranteed by design SBC in stop mode
PC33889
Tw-csb
15
40
90
us
Tw-spi Ts-1stspi
90 20
N/A N/A
us us
SBC in stop mode In stop mode after wake up
Figure 2. Timing Characteristics
Tpclk
CSB
Tlead Twclkh Tlag
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SCLK
Twclkl Tsisu Tsih
MOSI
Undefined
Tvalid
D0
Don't Care
D8
Don't Care
Tsodis
Tsoen
MISO
D0
Don't Care
D8
PC33889
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PC33889
3
CAN MODULE SPECIFICATION (COMPATIBLE WITH MC33388)
ELECTRICAL RATINGS Ratings
DC Voltage On Pins Tx, Rx DC voltage at V2 (V2int) DC Voltage On Pins CANH, CANL Transient Voltage At Pins CANH, CANL 0 < V2-int < 5.5V; Vsup 0; T < 500ms Transient Voltage On Pins CANH, CANL (Coupled Through 1nF Capacitor) DC Voltage On Pins Rth, Rtl Transient Voltage At Pins RtH, RtL 0 < V2-int < 5.5V; Vsup 0; T < 500ms RTH, RTL Termination Resistance
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Symbol
Vlogic V2int VBUS VCANH/VCANL Vtr Vrtl, Vrth VRtH/VRtL Rt
Min
-0.3 0 -20 -40
Typ
Max
VDD1 + 0.3 5.25 +27 40
Unit
V V V V
-150 -0.3 -0.3 500
100 +27 40 16000
V V V ohm
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ELECTRICAL CHARACTERISTICS (Vsup From 5.5V to 18V, V2int from 4.75 to 5.25V and Tj from -40C to 150C unless otherwise noted).
Conditions Symbol Min Typ Max Unit
Supply current described below are the CAN module internal supply current from internal V2 (V2-int) and Vsup Internal V2 Supply Current (CAN and SBC in Normal Mode). TX= 5V, CAN in Recessive State Internal V2 Supply Current (CAN and SBC in Normal Mode). TX = 0V, No Load, CAN in Dominant State Total supply Current (CAN in Receive Only Mode, SBC in Normal mode). Internal V2 = 5V; Vsup = 12V Internal V2 Supply Current (CAN in Bus TermVbat mode) Vsup = 12V TX Pin High Level Input Voltage Low Level Input Voltage TX High Level Input Current (Vi = 4V) TX Low Level Input Current (Vi = 1V) RX Pin High Level Output Voltage RX (I0 = -250A) Low Level Output Voltage (I0 = 1.5mA) CANH, CANL Pins Differential Receiver, Recessive To Dominant Threshold (By Definition, Vdiff=VCANH-VCANL) Vdiff1 -3.2 -2.5 V Voh Vol V2-int - 0.9 0 V2-int 0.9 V V Vih Vil ITX ITX 0.7*V2-int -0.3 -100 -100 -50 -50 V2-int+0.3V 0.3 * V2-int -25 -25 V V uA uA IV2-int 4 5.6 6.5 mA
IV2-int
4.2
5.8
6.7
mA
IV2-int + ISUP-int
1
1.4
mA
IV2-int
36
tbd
uA
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Conditions
Differential Receiver, Dominant To Recessive Threshold (Bus Failures 1, 2, 5) CANH Recessive Output Voltage TX = 5V; R(RTH) < 4k CANL Recessive Output Voltage TX =5V; R(RTL) < 4k CANH Output Voltage, Dominant TX = 0V; I CANH = -40mA; Normal Operating Mode CANL Output Voltage, Dominant TX = 0V; I CANL = 40mA; Normal Operating Mode CANH Output Current (VCANH = 0 ; TX = 0) CANL Output Current (VCANL = 14V; TX = 0) Detection Threshold For Short-circuit To Battery Voltage (Normal Mode) Detection Threshold For Short-circuit To Battery Voltage (Term Vbat Mode) CANH Output Current (Term Vbat Mode; VCANH = 12V, Failure3) CANL Output Current (Term Vbat Mode; VCANL = 0V; VBAT = 12V, Failure 4) CANL Wake Up Voltage Threshold CANH Wake Up Voltage Threshold Wake Up Threshold Difference (Hysteresis) CANH Single Ended Receiver Threshold (Failures 4, 6, 7) CANL Single Ended Receiver Threshold (Failures 3, 8) CANL Pull Up Current (Normal Mode) CANH Pull Down Current (Normal Mode) Receiver Differential Input Impedance CANH / CANL Differential Receiver Common Mode Voltage Range CANH To Ground Capacitance CANL To Ground Capacitance CCANL to CCANH Capacitor Difference (Absolute Value) RTH, RTL Pins RTL to V2-int Switch On Resistance (Iout < -10mA; Normal Operating Mode) RTL to BAT Switch Series Resistance (term Vbat Mode) RTH To Ground Switch On Resistance (Iout <10mA; Normal Operating Mode) Thermal Shutdown Rrtl 10 30 90 ohms ICANL
PC33889
Symbol
Vdiff2
Min
-3.2
Typ
Max
-2.5
Unit
V
VCANH
0.2
V
VCANL
V2-int - 0.2
V
VCANH
V2-int - 1.4
V
VCANL
1.4
V
ICANH ICANL VCANH, VCANL
50 50 7.3
75 90 7.9
100 130 8.9
mA mA V
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VCANH
VBAT/2 +3
VBAT /2+5
V
5
10
uA
0
2
uA
Vwake,L Vwake,H VwakeL-VwakeH VSE, CANH VSE, CANL ICANL,pu ICANH,pd Rdiff Vcom CCANH CCANL DCcan
2.5 1.2 0.2 1.5 2.8 45 45 100 -10
3 2
3.9 2.7
V V V
1.85 3.05 75 75
2.15 3.4 90 90 300 10 50 50 10
V V uA uA kohm V pF pF pF
Rrtl Rrth
8 10
12.5 30
20 90
kohm ohm
PC33889
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Conditions
CAN Module Thermal Shutdown
PC33889
Symbol
Tsd
Min
Typ
165
Max
Unit
C
AC CHARACTERISTICS (Vsup From 5.5V to 18V and Tj from -40C to 150C unless otherwise noted)
CANL and CANH Slew Rates (10% to 90%). Rising or Falling Edges. Note 1.Recessive to Dominant state. CANL and CANH Slew Rates (10% to 90%). Rising or Falling Edges. Note 1.Dominant to Recessive. Note 1. Propagation Delay TX to RX Low. Note 2. Propagation Delay TX to RX High. Note 2. Min. Dominant Time For Wake-up On CANL or CANH (Term Vbat; VSUP = 12V) Guaranteed by design. Failure 3 Detection Time (Normal Mode) Failure 6 Detection Time (Normal Mode) Failure 3 Recovery Time (Normal Mode) Failure 6 Recovery Time (Normal Mode) Failure 4, 7, 8 Detection Time (Normal Mode) Failure 4, 7, 8 Recovery Time (Normal Mode) Failure 4, 7,8 Detection Time, (Term Vbat; VSUP = 12V) Failure 3 Detection Time (Term Vbat; VSUP = 12V) Failure 3a Detection Time (Term Vbat; VSUP = 12V) Failure 4, 7,8 Recovery Time (Term Vbat; VSUP = 12V) Failure 3 Recovery Time (Term Vbat; VSUP = 12V) Failure 3a Recovery Time (Term Vbat; V SUP = 12V) Edge Count Difference Between CANH and CANL for Failures 1, 2, 5 Detection (Failure bit set, Normal Mode) Edge Count Difference Between CANH And CANL For Failures 1, 2, 5 Recovery (Normal Mode) TX Permanent Dominant Timer Disable Time (Normal Mode And Failure Mode) TX Permanent Dominant Timer Enable Time (Normal Mode And Failure Mode) Tsldr 2 8 V/us
Tslrd
2
9
V/us
TonRX ToffRX Twake 8
1 1 16
1.6 1.6 30
us us us
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Tdf3 Tdf6 Tdr3 Tdr6 Tdf478 Tdr478 Tdr47 Tdr3 Tdr3a Tdr47 Tdr3 Tdr3a Ecdf
10 50
30 200 160
80 500
us us us
150 0.75 10 0.8
200 1.5 30 1.2 3.84 2.3 1.92 1.2 1.92 3
1000 4 60 8
us ms us ms ms ms ms ms ms
Ecdr
3
tTX,d
0.75
4
ms
tTX,e
10
60
us
NOTE 1: Dominant to recessive slew rate is dependant upon the bus load characteristics. NOTE 2: AC Characteristics measured according to schematic figure 3.
PC33889
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Figure 3. Device Signal Waveforms
Tx high: RECESSIVE Bit VTX Tx low: DOMINANT Bit 5V CANL 3.6V Tx high: RECESSIVE Bit
PC33889
CANH
1.4V 0V 2.2V
Vth(dr)
0.7V -2.9V toffTX -5V
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Vdiff
Vth(rd)
VRX 0.7VCC tonRX toffRX 0.3VCC
t
RECESSIVE Bit DOMINANT Bit RECESSIVE Bit
Figure 4. Test Circuit for AC Characteristics
VDD
R
CANL
C
C
CANH
R
C
R = 100ohms C = 1nF
PC33889
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Freescale Semiconductor, Inc. DEVICE DESCRIPTION
4 DEVICE DESCRIPTION
Introduction: The MC33889 is an integrated circuit dedicated to automotive applications. It includes the following functions: - One full protected voltage regulator with 200mA total output current capability. - Driver for external path transistor for V2 regulator function. - Reset, programmable watchdog function - Four operational modes - Wake up capabilities: Forced wake up, cyclic sense and wake up inputs, CAN and SPI - Can low speed fault tolerant physical interface, compatible with Motorola MC33388D. 4.1 Device Supply The device is supplied from the battery line through the Vsup pin. An external diode is required to protect against negative transients and reverse battery. It can operate from 4.5V and under the jump start condition at 27V DC. This pin sustains standard automotive voltage conditions such as load dump at 40V. When Vsup falls below 3V typical the MC33889 detects it and store the information into the SPI register, in a bit called "BATFAIL". This detection is available in all operation modes. Vdd1 Voltage Regulator Vdd1 Regulator is a 5V output voltage with total current capability of 200mA. It includes a voltage monitoring circuitry associated with a reset function. The Vdd1 regulator is fully protected against over current, short-circuit and has over temperature detection warning flags and shutdown with hysteresis. V2 regulator V2 Regulator circuitry is designed to drive an external path transistor in order to increase output current flexibility. Two pins are used: V2 and V2 ctrl. Output voltage is 5V and is realized by a tracking function of the Vdd1 regulator. Recommended ballast transistor is MJD32C. Other transistor might be used, however depending upon PNP gain an external resistor capacitor network might be connected between emitter and base of PNP. The use of external ballast is optional (refer to simplified typical application). State of V2 is reported into IOR register (if V2 is below 4.5V typical in case of over load or short circuit). 4.4 HS1 Vbat Switch Output HS1 output is a 2 ohms typical switch from Vsup pin. It allows the supply of external switches and their associated pull up or pull down circuitry, in conjunction with the wake up input pins for example. Output current is limited to 200mA and HS1 is protected against short-circuit and has an over temperature shutdown (reported in IOR register). HS1 output is controlled from the internal register and SPI. It can be activated at regular intervals in sleep mode thanks to internal timer. It can also be permanently turned on in normal or stand-by modes to drive external loads such as relays or supply peripheral components. In case of inductive load drive external clamp circuitry must be added. Functional Modes The device has four modes of operation, stand-by, normal, stop and sleep modes. All modes are controlled by the SPI. An additional temporary mode called "normal request mode" is automatically accessed by the device (refer to state machine) after wake up events. Special mode and configuration are possible for software application debug and flash memory programming. 4.5.1 Normal mode: In this mode both regulators are ON and this corresponds to the normal application operation. All functions are available in this mode (watchdog, wake up input reading through SPI, HS1 activation, CAN communication). The software watchdog is running and must be periodically cleared through SPI. 4.5.2 Standby mode: Only the regulator 1 is ON. Regulator 2 is turned OFF by disabling the V2 ctrl pin. The CAN cell is not available, as powered from V2, other functions are available: wake up input reading through SPI, HS1 activation. The watchdog is running. 4.5.3 Sleep mode: Regulators 1 and 2 are OFF. In this mode, the MCU is not powered. In this mode, the device can be awakened internally by cyclic sense via the wake up inputs pins and HS1 output, from the forced wake function, the CAN physical interface, and SPI (CSB pin). 4.5.4 Stop mode Regulator 2 is turned OFF by disabling the V2 ctrl pin. The regulator 1 is activated in a special low power mode which allow to deliver 2 mA. The objective is to maintain the MCU of the application supplied while it is turned into power saving condition (i.e stop or wait mode). Stop mode is entered through SPI. Stop mode is dedicated to power the Microcontroller when it is in low power mode (stop, pseudo stop, wait etc.). In these mode the MCU supply current is less than 1mA. The MCU can restart its software application very quickly, without the complete power up and reset sequence. When the application is in stop mode (both MCU and SBC), the application can wake up from the SBC side (ex cyclic sense, forced wake up, CAN message, wake up inputs) or the MCU side (key wake up etc.). When Stop mode is selected by SPI, stop mode becomes active 20us after end of SPI message. The "go to stop" instruction must be the last instruction executed by the MCU before going to low power mode. 4.5 4.3 4.2
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Freescale Semiconductor, Inc. DEVICE DESCRIPTION
In stop mode the Software watchdog can be "running" or "not running" depending upon selection by SPI. Refer to SPI description, RCR register bit WDSTOP. If W/D is enabled the SBC must be wake up before W/D time expired, otherwise a reset is generated. In stop mode, SBC wake up capability are identical as in sleep mode. 4.5.4.1 Stop mode: wake up from SBC side, INT pin activation: When application is in stop mode, it can wake up from the SBC side. When a wake up is detected by the SBC (ex CAN, Wake up input, forced wake up etc.) the SBC turns itself into Normal request mode and activated the Vdd1 main regulator. When the main regulator is fully active, then the wake up is signalled to the MCU through the INT pin. INT pin is pulled low for 10us and then returns high. Wake up event can be read through the SPI registers. 4.5.4.2 Stop mode: wake up from MCU side: When application is in stop mode, the wake up event may come to the MCU. In this case the MCU has to signal to the SBC that it has to go into Normal mode in order for the Vdd1 regulator to be able to deliver full current capability. This is done by a low to high transition of the CSB pin. CSB pin low to high activation has to be done as soon as possible after the MCU. The SBC generates a pulse at INTB pin. Alternatively the L0 and L1 inputs can also be used as wake up from stop mode. 4.5.4.3 Stop mode current monitoring If the current in stop mode exceed the Idd1s-wu threshold, the SBC jumps into Normal request mode, activated the Vdd1 main regulator and generate and interrupt to the MCU. This interrupt is not maskable and not bit are set into the INT register. 4.5.4.4 Software watchdog in stop mode: If watchdog is enabled (register MCR, bit WDSTOP set), the MCU has to wake up independently of the SBC before the end of the SBC watchdog time. In order to do this the MCU has to signal the wake to the SBC through the SPI wake up (CSB pin low to high transition to activated SPI wake up). Then the SBC wakes up and jump into the normal request mode. MCU has to configure the SBC to go to either normal or standby mode. The MCU can then decide to go back again to stop mode. If no MCU wakes up occurs within the watchdog timing, the SBC will activate the reset pin and jump into the normal request mode. The MCU can then be initialized. 4.5.5 Normal request mode: This is a temporary mode automatically accessed by the device after a wake up event from sleep or stop mode or after device power up. In this mode the Vdd1 regulator is ON, V2 is off, the reset pin is high. As soon as the device enters the normal request mode an internal 350ms timer is started. During these 350ms the micro controller of the application must addressed the SBC via SPI and configure the watchdog register (TIM1 register). This is the condition for the SBC to leave the Normal request Mode and enter the Normal mode and to set the watchdog timer according to configuration done during the Normal Request mode. "BATFAIL flag" is a bit which is triggered when Vsup is below 3V. This bit is set into the MCR register. It is reset by MCR register read. 4.6 4.7 Internal Clock The device has an internal clock used to generate all timings (reset, watchdog, cyclic wake up, filtering time etc....).
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Reset pin A reset output is available in order to reset the microcontroller. The reset cause are: - Vdd1 falling out of range: if Vdd1 fall below the reset threshold (parameter Rst-th), the reset pin is pull low until Vdd1 return to nominal voltage. - Power on reset: at device power on or at device wake up from sleep mode, the reset is maintained low until Vdd1 is within its operation range. - Watchdog time out: if the watchdog is not cleared the SBC will pull the reset pin low for the duration of the reset duration time (parameter: reset-dur). For debug purposes at 25C, reset pin can be shorted to 5V. 4.8 Software watchdog (selectable window or time out watchdog) Software watchdog is used in the SBC normal and stand-by modes for the MCU monitoring. The watchdog can be either window or time out. This is selectable by SPI (register TIM, bit WDW). Default is window watchdog. The period for the watchdog is selectable by SPI from 5 to 350ms (register TIM, bits WDT0 and WDT1). When the window watchdog is selected, the closed window is the first half of the selected period, and the open window is the second half of the period. The watchdog can only be cleared within the open window time. An attempt to clear the watchdog in the closed window will generate a reset. Watchdog is cleared through SPI by addressing the TIM register. Refer to" table for reset pin operations operation in mode 2. Wake Up capabilities Several wake-up capabilities are available for the device when it is in sleep or stop mode. When a wake up has occurred, the wake up event is stored into the WUR or CAN registers. The MCU can then access to the wake up source. The wake up options are selectable trough SPI while the device is in normal or standby mode and prior to go to enter low power mode (sleep or stop mode). 4.9
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4.9.1 Wake up from wake up inputs (L0, L1) without cyclic sense: The wake up lines are dedicated to sense external switches state and if changes occur to wake up the MCU (In sleep or stop modes). The wake up pins are able to handle 40V DC. The internal threshold is 3V typical and these inputs can be used as input port expander. The wake up inputs state can be read through SPI (register WUR). L0 has a lower threshold than L1 in order to allow connection and wake up from a digital output such as a CAN physical interface for instance. 4.9.2 Cyclic sense wake up (Cyclic sense timer and wake up inputs L0, L1) The SBC can wake up upon state change of one of the wake up input lines (L0, L1) while the external pull up or pull down resistor of the switches associated to the wake up input lines are biased with HS1 Vsup switch. The HS1 switch is activated in sleep or stop mode from an internal timer. Cyclic sense and Forced wake up are exclusive. If Cyclic Sense is enabled the forced wake up can not be enabled. 4.9.3 Forced wake up The SBC can wake up automatically after a pre determined time spent in sleep or stop mode. Forced wake up is enabled by setting bit FWU in LPC register. Cyclic sense and Forced wake up are exclusive. If Forced wake up is enabled the Cyclic Sense can not be enabled. 4.9.4 CAN wake up The device can wake up from a CAN message. CAN wake up cannot be disabled. 4.9.5 SPI wake up The device can wake up by the CSB pin in sleep or stop mode. Wake up is detected by CSB pin transition from low to high level. In stop mode this correspond to the condition where MCU and SBC are both in Stop mode and when the application wake up events come through the MCU. 4.9.6 System power up At power up the device automatically wakes up. 4.10 SPI The complete device control as well as the status report is done through a 8 bits SPI interface. Refer to SPI paragraph. 4.11 CAN The device incorporates a low speed fault tolerant CAN physical interface. Speed rate is up to 125kBauds. Its electrical parameters for the CANL, CANH, Rtl, Rth Rx and Tx pins are compatible with the MC33388D. The state of the CAN interface is programmable through SPI. 4.12 Device power up, SBC wake up After device or system power up or a wake up from sleep mode, the SBC enters into "reset mode" then into "normal request mode". 4.13 Battery fall early warning: This function provides an Interrupt when the Vsup voltage is below 6.1V typical. This interrupt is maskable. An hysteresis is included. Operation is only in Normal and Standby modes. Vbat low state reported in IOR register. 4.14 Package and thermal consideration The device is proposed in a standard surface mount SO28 package. In order to improve the thermal performances of the SO28 package, 8 pins are internally connected to the lead frame and are used for heat transfer to the printed circuit board. 4.15 Table 1: Reset and Wdogb operation Figure below shows the reset and watchdog output operation. Reset is active at device power up and wake up. Reset is activated in case of Vdd1 fall or watchdog not triggered. Wdogb output is active low as soon as reset goes low and stays low as long as the watchdog is not properly re-activated by SPI.
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Figure 5. Reset and Wdogb function diagram Watchdog time out
Vdd1 Reset WDOGB SPI W/D clear SPI CSB Watchdog period
Watchdog register addressed The Wdogb output pin is a push pull structure than can drive external component of the application in order for instance to signal MCU wrong operation. Even if it is internally turned on (low sate) the reset pins can be forced to 5V at 25C only, thanks to its internal limited current drive capability. Wdogb stays low until the Watchdog register is properly addressed through SPI. 4.16 Debug mode Application hardware and software debug with the SBC. When the SBC is mounted on the same printed circuit board as the micro controller it supplies, both application software and SBC dedicated routine must be debugged. Following features allow the user to debug the software by allowing the possibility to disable the SBC internal software watchdog timer. 4.16.1 Device power up, reset pin connected to Vdd1 At SBC power up, the Vdd1 voltage is provided, but if no SPI communication occurs to configure the device, a reset occurs every 350ms. In order to allow software debug and avoid MCU reset the Reset pin can be connected directly to Vdd1 by a jumper. 4.16.2 Debug modes with software watchdog disabled though SPI (Normal Debug, Standby Debug and Stop Debug) The software watchdog can be disabled through SPI. In order to avoid unwanted watchdog disable and to limit the risk of disabling the watchdog during SBC normal operation the watchdog disable has to be done with the following sequence: Step 1) Power down the SBC Step 2) Power up the SBC (The BATFAIL bit is set, and the SBC enters normal request mode) Step 3) Write to TIM1 register to allow SBC to enter Normal mode Step 4) Write to MCR register with data 0000 (this enables the debug mode). (Complete SPI byte: 000 1 0000) Step 5) Write to MCR register normal debug (0001 x101), standby debug (0001 x110) or Stop debug (0001 x111) While in debug mode, the SBC can be used without having to clear the W/D on a regular basis to facilitate software and hardware debug. Step 6) To leave the debug mode, write 0000 to MCR register. To avoid entering debug mode after a power up, first read BATFAIL bit (MCR read) and write 0000 into MCR. The graph below illustrates the debug mode entering. Figure 6. Debug mode enter VSup Vdd1 Batfail
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TIM1(step 3) SPI
MCR (step5) SPI: read batfail
MCR (step6)
MCR(step4) debug mode
SBC in debug Mode, no W/D
SBC not in debug Mode and W/D on
4.16.3 MCU flash programming configuration In order to allow the possibility to download software into the application memory (MCU EEPROM or Flash) the SBC allows the following capabilities: The Vdd1 can be forced by an external power supply to 5V and the reset and Wdogb outputs by
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external signal sources to zero or 5V and this without damage. This allow for instance to supply the complete application board by external power supply and to apply the correct signal to reset pins. 4.17 Gnd Shift Detection
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4.17.1 General When normally working in two-wire operating mode, the CAN transmission can afford some ground shift between different nodes without trouble. Nevertheless, in case of bus failure, the transceiver switches to single-wire operation, therefore working with less noise margin. The affordable ground shift is decreased in this case. The SBC provides a ground shift detection for diagnosis purpose. Four ground shift levels are selectable and the detection is stored in the IOR register which is accessible via the SPI. 4.17.2 Detection Principle The gnd shift to detect is selected via the SPI out of 4 different values (-0.5V, -1V, -1.5V, -2V). At each TX falling edge (end of recessive state) CANH voltage is sensed. If it is detected to be below the selected gnd shift threshold, the bit SHIFT is set at 1 in IOR register. No filter is implemented. Required filtering for reliable detection should be done by software (e.g. several trials).
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PC33889
5
TABLE OF OPERATION
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The table below describe the SBC operation modes. Voltage Regulator HS1 switch Vdd1: ON V2: OFF HS1: OFF Vdd1: ON V2: ON HS1 controllable Vdd1: ON V2: OFF HS1 controllable Vdd1: ON (limited current capability) V2: OFF HS1: OFF or cyclic Vdd1: OFF V2: OFF HS1 OFF or cyclic CAN (always enable) SPI and L0,L1 Cyclic sense or Forced Wake up CAN (always enable SPI and L0,L1 Cyclic sense Forced Wake up Wake up capabilities (if enabled)
mode
Reset pin
INT
Software Watchdog
CAN cell
Normal Request
Low for 1ms, then high If enabled, signal failure (Vdd pre warning temp, CAN, HS1) If enabled, signal failure (Vdd temp, HS1)
term Vbat
Normal
Normally high. Active low if W/D or Vdd1 under voltage occur
Running
Term Vbat Tx/Rx Rec only
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Standby
Normally high. Active low if W/D or Vdd1 under voltage occur
Running
Term Vbat Tx/Rx Rec only
Stop
Normally high. Active low if W/D or Vdd1 under voltage occur
Signal SBC wake up (not maskable)
- Running if enabled - Not Running if disabled
Term Vbat.
Sleep
Low
Not active
No Running
Term Vbat.
Tableau 1 : table of operation
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SIMPLIFIED STATE MACHINE
W/D: timeout OR Vdd1 low W/D: timeout & Nostop & !BATFAIL Reset counter (1ms) expired 2 SPI: standby & W/D trigger (note1) 3
1
Reset
W /D :t im
Normal Request
1 Vdd1 low OR W/D: time out 350ms & !Nostop
eo ut O
Standby
Nostop & SPI: sleep & CSB low to high transition Nostop & SPI: sleep & CSB low to high transition
SBC power up
S to PI: hi St gh o tra p & ns C itio SB n
lo w
4
SPI: standby 1
d1
Wake up
R
Vd
lo
w
(n o
Power Down
te
2)
2 1
Stop
W/D: timeout OR Vdd1 low
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SPI: Stop & CSB low to high transition
Normal
Wake up (Vdd1 high temperature OR (Vdd1 low > 100ms & Vsup >BFew)) & Nostop & !BATFAIL
SPI: normal
W /D rig :T ge r
Sleep
1 2 3 4 denotes priority State machine description: "Nostop" means Nostop bit = 1 "! Nostop" means Nostop bit = 0 "BATFAIL" means Batfail bit = 1 "! BATFAIL" means Batfail bit = 0 "Vdd1 over temperature" means Vdd1 thermal shutdown occurs "Vdd1 low" means Vdd1 below reset threshold "Vdd1 low > 100ms" means Vdd1 below reset threshold for more than 100ms "W/D: Trigger" means TIM1 register write operation. Vsup>BFew means Vsup > Battery Fall Early Warning (6.1V typical)
"W/D: time out" means TIM1 register not written before W/D time out period expired, or W/D written in incorrect time window if window W/D selected (except stop mode). In normal request mode time out is 355ms p2.2 (350ms p3)ms. "SPI: Sleep" means SPI write command to MCR register, data sleep "SPI: Stop" means SPI write command to MCR register, data stop "SPI: Normal" means SPI write command to MCR register, data normal "SPI: Standby" means SPI write command to MCR register, data standby Note 1: these 2 SPI commands must be send in this sequence and consecutively. Note 2: if W/D activated
Behavior at SBC power up
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Transitions to enter debug modes
W/D: time out 350ms
Normal Request
W/D: Trigger
Reset counter (1ms) expired
Reset
Power Down
Normal
SPI: MCR (0000) & Normal Debug
Normal Debug
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SPI: MCR (0000) & Standby Debug
Standby Debug
Simplified State machine in debug modes
W/D: time out 350ms
Stop (1)
Wake up
Normal Request
SPI: standby & W/D: Trigger R
Reset counter (1ms) expired
Reset
Wake up
Sleep
& !BATFAILNOSTOP & SPI: Sleep
R
up
W/
D:
Trig g
R
er
W ak
e
R
R
R
SPI: Stop
SPI: Stop debug &CSB low to high transition
SPI: standby debug
E
E
SPI: Standby debug
Standby Debug
SPI: Normal debug
Normal Debug
R
R
(1) If stop mode entered, it is entered without watchdog, no matter the WDSTOP bit. (E) debug mode entry point (step 5 of the debug mode entering sequence). (R) represents transitions to reset mode due to Vdd1 low.
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SPI: Normal Debug
SP I: St an
de bu g
db
y
I: n or
ma l
D eb
ug
Stop debug
Standby
SP
Normal
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PC33889
6
TYPICAL APPLICATIONS
Freescale Semiconductor, Inc.
Q1 Vbat V2CTRL Vsup V2
5V
Vsup monitor CAN supply Dual Voltage Regulator 5V/200mA Vdd1 Monitor Mode control
HS1 control
Vdd1
5V/200mA
HS1
L0 L1
Oscillator
Programmable wake-up input
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Interrupt Watchdog Reset
INTB WDOGB
Reset
MOSI SCLK MISO CSB V2 Txd Rxd Gnd
SPI Interface
Rrth Rth CAN H CAN L Rrtl Rtl Low Speed 125Kbit/s Fault Tolerant CAN Physical Interface
Fig 1: Simplified typical application with ballast transistor
5V/100mA
Vbat V2CTRL (open) Vsup V2
Vsup monitor Dual Voltage Regulator Vdd1 Monitor
CAN supply
5V/200mA
Vdd1 5V/100mA
Mode control
HS1 control
HS1
L0 L1
Oscillator
Programmable wake-up input
Interrupt Watchdog Reset
INTB WDOGB
Reset
MOSI SCLK MISO CSB V2 Txd Rxd Gnd
SPI Interface
Rrth Rth CAN H CAN L Rrtl Rtl Low Speed 125Kbit/s Fault Tolerant CAN Physical Interface
Fig 2: Simplified typical application without ballast transistor
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7
7.1
PC33889
SPI INTERFACE
Data format description Bit7 MISO A2 Bit6 A1 Bit5 A0 Bit4 R/W Bit3 D3 Bit2 D2 Bit1 D1 Bit0 D0 MOSI Read operation: R/W bit = 0 Write operation: R/W bit = 1
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address data The SPI is a 8 bit SPI. First 3 bits are used to identify the internal SBC register address, bit 4 is a read/write bit. The last 4 bits are data send from MCU to SBC or read back from SBC to MCU. During write operation state of MISO has no signification. During read operation only the last 4 bits at MISO have a meaning (content of the accessed register) Following tables describe the SPI register list, and register bit meaning. Registers "reset value" is also described, as well as the "reset condition". reset condition is the condition which cause the bit to be set at the "reset value". Possible reset condition are: Power On Reset: POR NR2R - Normal Request to Reset mode SBC mode transition: NR2N - Normal Request to Normal mode N2R - Normal to Reset mode STB2R - Standby to Reset mode STO2R - Stop to Reset mode SBC mode: List of Registers Name MCR Adress $000 Description Mode control register Comment and usage Write: Control of normal, standby, sleep, and stop modes Read: BATFAIL flag and other status bits and flags Write: Configuration of reset voltage level, WD in stop mode, low power mode selection Read: CAN wake up event, Tx permanent dominant Write: CAN module control: Tx/Rx, Rec only, term Vbat, Normal and extended modes, filter at L0 input. Read: CAN failure status bits Write: HS1 (high side switch) control in normal and standby mode. Gnd shift register level selection Read: HS1 over temp bit, SHIFT bit (gnd shift above selection), Vsup below 6.1V, V2 below 4V Write: Control of wake up input polarity Read: Wake up input, and real time Lx input state Write: TIM1, Watchdog timing control, window or Timeout mode. Write: TIM2, Cyclic sense and force wake up timing selection Write: HS1 periodic activation in sleep and stop modes Force wake up control Write: Interrupt source configuration Read: INT source RESET - SBC in Reset mode
RCR
$001
Reset control register
CAN
$010
CAN control register
IOR
$011
I/O control register
WUR TIM LPC INTR Table 7-1.
$100 $101 $110 $111
Wake up input register Timing register Low power mode control register Interrupt register
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7.2 7.2.1 Register description MCR Register MCR W $000b R Reset Reset condition Table 7-2. Control bits MCTR2 MCTR1 MCTR0 SBC mode Description To enter debug mode, SBC must be in Normal or Standby mode and BATFAIL(1) must be still at 1. To leave debug mode, BATFAIL must be at 0. BATFAIL 0 VDDTEMP 0 POR, RESET GFAIL 0 POR, RESET WDRST 0 POR, RESET D3 D2 MCTR2 D1 MCTR1 D0 MCTR0
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0
0
0
Enter/leave debug mode
0 0 0 0 1 1 1 1
0 1 1 1 0 0 1 1
1 0 1 1 0 1 0 1
Normal Standby Stop, watchdog off (2) Stop, watchdog on (2) Sleep (3) Normal Standby Stop No watchdog running, debug mode
(1): Bit BATFAIL cannot be set by SPI. BATFAIL is set when Vsup falls below 3V. (2): Watchdog ON or OFF depends upon RCR register bit D3. (3): Before entering sleep mode, bit NOSTOP in RCR register must be previously set to 1. Status bits Status bit GFAIL BATFAIL VDDTEMP WDRST Description Logic OR of CAN failure, HS1 failure, V2LOW Battery fail flag (Vsup<3V) Temperature pre-warning on VDD (latched) Watchdog reset occurred
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7.2.2 RCR register RCR W $001b R Reset Reset condition Table 7-3. Control bits 1 POR, RESET 0 POR, NR2N TXFAILURE CANWU 0 POR D3 WDSTOP D2 NOSTOP D1 D0 RSTTH
PC33889
Status bit WDSTOP
Bit value 0 1 0
Description No watchdog in stop mode Watchdog runs in stop mode Stop mode is default low power mode Sleep mode is default low power mode Reset threshold 1 selected (typ 4.6V) Reset threshold 2 selected (typ 4.2V) Wake from CAN Tx permanent dominant (CAN)
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NOSTOP 1 0 RSTTH 1 CANWU TXFAILURE 7.2.3 CAN register Some description. CAN W $010b R Reset Reset condition Table 7-4. Fault tolerant CAN transceiver standard modes The CAN transceiver standard mode can be programmed by setting CEXT to 0. The transceiver cell will then be behave as known from MC33388. CEXT 0 0 0 0 Table 7-5. Fault tolerant CAN transceiver extended modes CCTR1 0 0 1 1 CCTR0 0 1 0 1 RxOnly RxTx Mode TermVBAT CS3 0 POR, CAN CS2 0 POR, CAN CS1 0 POR, CAN CS0 0 POR, CAN D3 FDIS D2 CEXT D1 CCTR1 D0 CCTR0 1 1
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By setting CEXT to 1 the transceiver cell supports sub bus communication. CEXT 1 1 1 1 Table 7-6. FDIS 0 1 L0 wake input filter (20us typical) Enable (LO wake threshold selectable by WUR register) Disable (L0 wake up threshold is low level only, no matter D0 and D1 bits set in WUR register). CCTR1 0 0 1 1 CCTR0 0 1 0 1 Mode TermVBAT TermVDD RxOnly RxTx
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note: if DFIS bit is set to 1, WUR register must be read before going into sleep or stop mode in order to clear the wake up flag. During read out L0 must be at high level and should stay high when entering sleep or stop. Status bits CS3 0 0 0 0 0 1 1 1 1 CS2 0 0 1 1 1 0 1 1 1 CS1 0 0 0 1 1 0 0 1 1 CS0 0 1 1 0 1 1 1 0 1 1 5 8, 3a 3 2 4, 7 9 6 CANL short circuit to CANL open wire ground / CANL VDD VBAT CANH short circuit to Bus failure # no failure CANH open wire ground VDD VBAT Description
comments: CS2 bit at 0 = open failure. CS2 bit at 1 = short failure. (CS3 bit at 0 and (CS1 = 1 or CS2 =1)) = CANH failure. CS3 bit at 1 = CANL failure. CS1 and CS0 bits: short type failure coding (gnd, Vdd or Vbat). In case of multiple failures, the last failure is reported. 7.2.4 IOR register Some description. IOR W $011b R Reset Reset condition Table 7-7. SHIFT HS1OT 0 POR, RESET V2LOW 0 POR, RESET VSUPLOW 0 POR, RESET D3 D2 HS1ON D1 GSLR1 D0 GSLR0
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Control bits HS1ON 0 1 Table 7-8. HS1 HS1 switch turn OFF HS1 switch turn ON
GSLR1 0 0 1 1
GSLR0 0 1 0 1
typical gnd shift comparator level -0.5 V -1 V -1.5 V -2 V
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Table 7-9. gnd shift selection
SHIFT 0 1
state Gnd shift value is lower GSLR1 and GSLR2 selection Gnd shift value is higher GSLR1 and GSLR2 selection
Status bits Status bit HS1OT (*) SHIFT V2LOW VSUPLOW Description High side 1 over temperature gnd shift level selected by GSLR1 and GSLR2 bits is reached V2 below 4V typical Vsup below 6.1V typical
(*) Once the HS1 switch has been turned off because of over temperature, it can be turned on again by setting the appropriate control bit to "1".
7.2.5 WUR register The local wake-up inputs L0 and L1 can be used in both normal and standby mode as port expander and for waking up the SBC in sleep or stop mode. WUR W $100b R Reset Reset condition Table 7-10. L1WUb 1 L1WUa 1 L0WUb 1 L0WUa 1 D3 LCTR3 D2 LCTR2 D1 LCTR1 D0 LCTR0
POR, NR2R, N2R, STB2R, STO2R
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PC33889
Control bits:. LCTR3 X X X X 0 0 1 1 Table 7-11. Status bits: LCTR2 X X X X 0 1 0 1
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LCTR1 0 0 1 1 X X X X LCTR0 0 1 0 1 X X X X L0 configuration inputs disabled high level sensitive low level sensitive both level sensitive inputs disabled high level sensitive low level sensitive both level sensitive L1 configuration
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L0WUb 0 1 0
L0WUa 0 1 1
FDIS bit in CAN register 0 0 1
Description No wake up occurred at L0 (sleep or stop mode). Low level state on L0 (standby or normal mode) Wake up occurred at L0 (sleep or stop mode). High level state on L0 (standby or normal mode) Wake up occurred at L0 (sleep or stop mode with L0 filter disable). WUR must be set to xx00 before sleep or stop mode.
L1WUb 0 1
L1WUa 0 1
Description No wake up occurred at L1 (sleep or stop mode). Low level state on L1 (standby or normal mode) Wake up occurred at L1 (sleep or stop mode). High level state on L1 (standby or normal mode)
7.2.6 TIM registers Description: This register is splitted into 2 sub registers, TIM1 and TIM2. TIM1 controls the watchdog timing selection as well as the window or time out option. TIM1 is selected when bit D3 is 0. TIM2 is used to define the timing for the cyclic sense and forced wake up function. TIM2 is selected when bit D3 is 1. No read operation is allowed for registers TIM1 and TIM2
7.2.7 TIM register Description. TIM1 W $101b R Table 7-12. D3 0 D2 WDW D1 WDT1 D0 WDT0
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TIM1 Reset Reset condition Table 7-12. Description WDW 0 0 0 0 1 1 1 1 Table 7-13. jWatchdog operation (window and time out) window closed window open for watchdog clear no watchdog clear allowed WDT1 0 0 1 1 0 0 1 1 WDT0 0 1 0 1 0 1 0 1 Watchdog timing [ms] 10 50 no window watchdog 100 350 10 50 100 350 window watchdog enabled (window lenght is half the watchdog timing) D3 D2 0 POR, RESET D1 0 POR, RESET D0 0 POR, RESET
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window open for watchdog clear
WD timing * 50%
WD timing * 50% Watchdog period (WD timing selected by TIM 2, bit WDW=0) Time out watchdog
Watchdog period (WD timing selected by TIM 2 bit WDW=1) Window watchdog
7.2.8 TIM2 register The purpose of TIM2 register is to select an appropriate timing for sensing the wake-up circuitry or cyclically supplying devices by switching on or off HS1 TIM2 W $101b R Reset Reset condition Table 7-14. 0 POR, RESET 0 POR, RESET 0 POR, RESET D3 1 D2 CSP2 D1 CSP1 D0 CSP0
CSP2 0 0 0 Table 7-15.
CSP1 0 0 1
CSP0 0 1 0
Cyclic sense timing [ms] 5 10 20
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CSP2 0 1 1 1 1 Table 7-15. CSP1 1 0 0 1 1 CSP0 1 0 1 0 1 Cyclic sense timing [ms] 40 75 100 200 400
Cyclic sense on time
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Cyclic sense timing 10s to 20us HS1 sample t 7.2.9 LPC register Description: This register controls: - The state of HS1 in stop and sleep mode (HS1 permanently off or HS1 cyclic) - Enable or Disable the forced wake up function (SBC automatic wake up after time spend in sleep or stop mode, time defined by TIM2 register) - Enable or disable the sense of the wake up inputs (Lx) at sampling point of the cyclic sense period (LX2HS1 bit).
LPC W $110b R Reset Reset condition Table 7-16.
D3 LX2HS1
D2 FWU
D1 IDDS
D0 HS1AUTO
0 POR, NR2R, N2R, STB2R, STO2R
0 POR, NR2R, N2R, STB2R, STO2R
0 POR, NR2R, N2R, STB2R, STO2R
0 POR, NR2R, N2R, STB2R, STO2R
LX2HS 1 X X 0 1 Table 7-17.
HS1AUTO 0 1 X X
Wake-up inputs supplied by HS1
Autotiming HS1 off on, HS1 cyclic, period defined in TIM2 register
no yes, Lx inputs sensed at sampling point
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PC33889
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Bit FWU IDDS Description If this bit is set, and the SBC is turned into sleep or stop mode, the SBC wakes up after the time selected in the TIM2 register Bit = 0: Idds-wu1 selected (lowest value, typ 3.5mA) Bit = 1: Idds-wu2 selected (highest value, typ 14mA)
7.2.10
INTR register
INTR W $111b R Reset Reset condition Table 7-18. Control bits: Control bit CANF VDDTEMP HS1OT-V2LOW VSUPLOW
D3 VSUPLOW VSUPLOW 0 POR, RESET
D2 HS1OT-V2LOW HS1OT 0 POR, RESET
D1 VDDTEMP VDDTEMP 0 POR, RESET
D0 CANF CANF 0 POR, RESET
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Description Mask bit for CAN failures (OR of any CAN failure) Mask bit for VDD medium temperature Mask bit for HS1 over temperature OR V2 below 4V Mask bit for sup below 6.1V
When the mask bit has been set, INTB pin goes low if the appropriate condition occurs. Status bits: Status bit CANF VDDTEMP HS1OT VSUPLOW Description CAN failure VDD medium temperature HS1 over temperature Vsup below 6.1V typical
Notes: If HS1OT-V2LOW interrupt is only selected (only bit D2 set in INTR register), reading INTR register bit D2 leads to two possibilities: Bit D2 = 1: INT source is HS1OT Bit D2 = 0: INT source is V2LOW. Upon a wake up condition from stop mode due to over current detection (Idd1s-wu1 or Idd1s-wu2), an INT pulse is generated, however INTR register contain remains at 0000 (not bit set into the INTR register).
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CASE OUTLINE
PC33889
A
D
28 15
M
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 4. MAXIMUM MOLD PROTRUSION 0.015 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 2.35 2.65 0.13 0.29 0.35 0.49 0.23 0.32 17.80 18.05 7.40 7.60 1.27 BSC 10.05 10.55 0.41 0.90 0_ 8_
E
H
1 14 PIN 1 IDENT
B
0.25
M
B
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L 0.10
SEATING PLANE
e B 0.025
M
C
DIM A A1 B C D E e H L
A1
A
C CA
S
q
q
B
S
CASE 751F-05 ISSUE F
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